1. Technical Field
The present invention relates generally to the field of semiconductor device formation, and more specifically to structures which interconnect a plurality of metal wiring layers by incorporating dummy shapes and voids therein, as well as to the method by which such structures may be manufactured.
2. Related Art
Copper damascene (i.e., etching) processes are incompatible with some aspects of industry standard aluminum-based design layouts. Specifically, wide metal lines, wide regions devoid of metal wires (i.e., xe2x80x9cwhitespacexe2x80x9d), local regions of high metal-pattern-density, and local regions of low metal-pattern-density are all incompatible with state of the art in copper damascene processing. Consequently, the interconnect levels of semiconductor designs must be redrawn in order to accommodate the aforementioned limitations of damascene copper, specifically by following maximum-linewidth rules, wide-line/wide-space rules, and local metal-pattern-density rules. These constraints on interconnect layouts are a significant obstacle to the utilization of damascene copper processes.
The related art generally uses one of two methods to produce a connection between areas of high via concentration (i.e., xe2x80x9cvia farmsxe2x80x9d) and copper damascene layers in a semiconductor device. These two methods differ in their respective approaches to existing via farms. The first method does not allow any via farms, while the second method rebuilds most or all of the via farms.
In the first method, via farms are not allowed. Instead, only a single row of vias is allowed around the perimeter of the intersection of wide metal lines. This approach requires that industry-standardized designs be manually adjusted to remove xe2x80x9cfarmxe2x80x9d vias, and subsequently retimed because the total via resistance for a large farm can be much less than the total via resistance for a single ring of vias along the perimeter.
The second method requires the rebuilding of all via farms. A design tool may be applied to the semiconductor device design. The design tool, such as those known in the art, may identify intersections of wide metal connected by vias, remove all vias from the intersection, and replace the vias in a preferred configuration (e.g., a single or double row at the perimeter of the intersection). However, there are two major drawbacks with this method. First, a large proportion of the via shapes are removed from any large via farm. Second, the design data is altered. Removing and replacing a large number of via shapes can have an unpredictable effect, both on the run-time, and on the results of subsequent verification procedures such as Design is Rule Checking (DRC) and Logical Versus Schematic (LVS) checking.
The invention disclosed herein presents a process and related structures that allow migration of industry-standard aluminum-based layouts to copper damascene, based solely on shapes-information (i.e., no net-list analysis is required). This method and its attendant structures have the added property of leaving all the customer""s design shapes unaltered. Fill shapes for metal layer xe2x80x9cxxe2x80x9d (MxFILL) and hole shapes for metal layer xe2x80x9cxxe2x80x9d (MxHOLE) are added to the design (where xe2x80x9cxxe2x80x9d denotes the number of a layer), but the customer""s shapes and the hierarchy of the customer""s design are left unaltered.
Specifically, metal fill shapes (i.e., small electrically-isolated xe2x80x9cdummyxe2x80x9d metal shapes that are placed in otherwise empty regions), and metal hole shapes (i.e., small isolated xe2x80x9cholesxe2x80x9d that are cut from the interior of wide metal lines) are used to satisfy all of the copper damascene-specific ground rules.
By judicious choice of the size and placement of these fill and hole shapes, it is possible to make their addition virtually transparent to the customer""s design. That is, the electrical behavior of a design utilizing both metal fill and metal hole shapes can be made to behave in a manner entirely consistent with modeled electrical behavior of the design without regard to the specific placement of fill and hole shapes.
The present invention provides a method to produce a connection between via farms and copper damascene layers in a semiconductor device by initially deriving via farms, and next allowing MxHOLE shapes to be placed on the interior of via farms without regard to the exact location of the vias located there.
The present invention can be fully automated, is entirely shapes-based (i.e., does not require net-list building), leaves the customer""s design data unaltered (only adding shapes to MxFILL and MxHOLE), and preserves the majority of the via and hole area within the interior of so-defined via farms. This approach transparently accommodates a wide variety of via farm layouts, and by construction satisfies the via electromigration requirements for wide copper lines. Furthermore, because a xe2x80x9ctypicalxe2x80x9d via is at the end of a minimum-width wire, and contacts the end of another minimum-width wire below, the nominal via resistance is quite high, and the tolerance, particularly for high resistance is very large. Most of the factors that tend to increase the resistance of a typical via are not applicable to a via which is fully landed in a wide metal layer. Indeed, the specified nominal resistance of a via farm will generally be much greater than the measured resistance of the via farm, even with a fraction of the interior vias landing on metal holes.
The present invention provides an electronic circuit comprising: a semiconductor substrate; a dielectric material such as oxide positioned on said semiconductor substrate, said dielectric having at least one cavity therein; a metal layer positioned on said semiconductor substrate within said at least one cavity; and a plurality of cavities within said metal layer, each cavity or cavities having a layer of said dielectric material positioned therein.
The present invention additionally provides an electronic circuit comprising: a semiconductor substrate; a first metal conductor on said semiconductor substrate; a second metal conductor on said semiconductor substrate; and a plurality of metal forms on said first and said second metal conductors, said plurality of metal forms insulated from said first and second metal conductors.
The present invention also provides a method of manufacturing a semiconductor device comprising: providing at least two metal layers over a substrate, the metal layers being isolated from each other by an insulating layer and forming a contact/via within the dielectric layer to electrically connect at least two of the metal layers, wherein a contact/via array comprises a plurality of contact/via columns and a plurality of contact/via rows made up of a plurality of contacts/vias; generating hole and fill information for a preferred design; creating a metal fill shapes pattern; creating a metal hole shapes pattern; verifying a resultant design which incorporates the metal fill shapes pattern and the metal hole shapes pattern; verifying the compatibility of original design data for the semiconductor device with the resultant design.